It is common to add functionality to the node of a circuit module, particularly for testing circuit arrangements. One conventional testing protocol is set forth in the Joint Testing Action Group (JTAG) IEEE 1149.1 standard. IEEE standard 1149.1 (hereinafter "JTAG") was developed as a specification for a standardized serial test bus for testing integrated circuit components or circuit modules and their interconnections on a printed circuit board, as well as for observing or modifying circuit activity during normal operation of the components. The JTAG test access port logic is entirely separate from the core circuit module operation on an integrated circuit device, and is accessed by five unique and dedicated component pins. The JTAG standard defines how the logic must function to be standard compliant. Implementation of a JTAG testing circuit at a node of a circuit module adds functionality to that node.
However, adding functionality to a node of a circuit module, e.g., to implement JTAG, involves the use of additional logic functions, such as, e.g., multiplexers (MUXs), and NAND and NOR gates. The additional logic functions add a load to the circuit which causes propagation delays in the normal or non-JTAG testing mode of the circuit module. The increase in propagation delays slows down the performance of the circuit. Therefore, there is a need to add functionality to a node of a circuit module, such as for implementing JTAG or non-JTAG testing, while reducing propagation delays.